Single poly EEPROM is widely used as nonvolatile memory for embedded applications in CMOS logic and mixed signal circuits. The single poly EEPROM cell is fully compatible with standard single poly CMOS processes and it is often called "zero cost" EEPROM.
A conventional prior art EEPROM cell is shown in FIGS. 1-3. A large n-well 103 serves as a "control gate" for the EEPROM cell because it is capacitively coupled to the floating gate which is formed from a layer of polysilicon. The p+ region 105 near the edge of the floating gate is shorted with the n+ well contact 107. This allows the n-well surface beneath the floating gate to be easily inverted during programming operation. The n-channel transistor (seen in cross section of FIG. 3) is used for the read operation and its threshold voltage is modulated by the presence or absence of electron charge on the floating gate. By this method, digital information can be stored in the EEPROM cell.
The cell can be programmed (electrons injected onto the floating gate) using the well known channel hot electron (CHE) injection by applying approximately 10-12 volts at the control gate (V.sub.cg) and approximately 6 volts at the drain of the n-channel transistor. After programming, the cell threshold voltage increases from about 1.5 volts to 7 volts. Thus, for read operation, by applying 5 volts on the control gate and approximately 1 volt at the drain, the cell is either "off" or "on" representing the digital information "0" or "1", respectively.
One difficulty with this prior art cell is that relatively high voltages are necessary to operate the EEPROM cell. The prior art is also large in size. What is needed is a low voltage single poly EEPROM cell with small size.